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Each DDC consists of multiple signal processing stages: a bit frequency translator numerically controlled oscillator NCO , and decimation filters. The user can configure the Subclasss 1 JESDB-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. This product may be protected by one or more U.

The AD is a dual, bit, 1. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. Each DDC consists of up to five cascaded signal processing stages: a bit frequency translator NCO , and four half-band decimation filters.

The DDCs are bypassed by default. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. Users can configure the Subclass 1 JESDB-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. All of these features can be programmed using a 1. It consists of two, bit 1. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz.

The device is designed for sampling wide bandwidth analog signals of up to 1. Each DDC consists of four cascaded signal processing stages: a bit frequency translator NCO and four half-band decimation filters. Users can configure the Subclass 1 JESDB-based high speed serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. Each DDC consists of four cascaded signal processing stages: a bit frequency translator NCO , and four half-band decimation filters. Users can configure the Subclass 1 JESDB-based high speed serialized output in a variety of one-, two-, or four-lane con-figurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device.

Buffered inputs with programmable input termination eases filter design and implementation.

What we offer

Two integrated wideband decimation filters and numerically controlled oscillator NCO blocks supporting multiband receivers. Flexible serial port interface SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. This device is designed for sampling wide bandwidth analog signals of up to 1. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The analog inputs and clock signals are differential inputs.

Each DDC consists of up to five cascaded signal processing stages: a bit frequency translator, NCO, and up to four half-band decimation filters. Users can configure each pair of intermediate frequency IF receiver outputs onto either one or two lanes of Subclass 1 JESDB-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. All of these features can be pro-grammed using the 1. This device is designed to support communications applications. The analog full power bandwidth of the device is 1. The AD is optimized for wide input bandwidth, excellent linearity, and low power in a small package.

Full Gauge Controls

The analog inputs and clock signal input are differential. The device supports two different output modes selectable via the serial port interface SPI. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask based on DPD applications are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed.

For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESDB-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. All of these features can be programmed using the 1. This product is designed for sampling wide bandwidth analog signals.

Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. Each ADC data output is internally connected to an optional decimate-by-2 block. The AD has several functions that simplify the automatic gain control AGC function in a communications receiver.

Data Converters for Wireless Standards

Users can configure the Subclass 1 JESDB-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. The AD is a bit monolithic sampling analog-to-digital converter ADC that operates at conversion rates of up to 2. This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone.


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The JESDB-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The AD is a quad, bit, MSPS analog-to-digital converter ADC with an on-chip sample and hold circuit designed for low cost, low power, small size, and ease of use.

The device operates at a conversion rate of up to MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1. An external reference or driver components are not required for many applications. Individual channel power-down is supported and typically consumes less than 14 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation.

The available digital test patterns include built-in deterministic and pseudo-random patterns, along with custom user-defined test patterns entered via the serial port interface SPI. The AD is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges.

A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESDB high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. These outputs are at CML voltage levels. However, if data is sent through one lane, a sampling rate of up to MSPS is supported. Flexible power-down options allow significant power savings, when desired.

Programmable overrange level detection is supported for each channel via the dedicated fast detect pins. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface. The AD supports communications applications where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features wide bandwidth inputs supporting a variety of user-selectable input ranges.

A duty cycle stabilizer DCS is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. Data can be sent through the lane at the maximum sampling rate of MSPS, which results in a lane rate of 5 Gbps. Programmable overrange level detection is supported via the dedicated fast detect pins. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between The bit complex output data is transferred to the host via a single or dual lane JESDB interface supporting line rates of up to 5.

The AD is an bit, MSPS, dual-channel intermediate frequency IF receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. The device consists of two high performance analog-to-digital converters ADCs and noise shaping requantizer NSR digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline.

A duty cycle stabilizer DCS compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The device supports two different output modes selectable via the SPI.

What we offer

With the NSR feature enabled, the outputs of the ADCs are processed such that the AD supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an bit output resolution. The AD can achieve up to This allows the AD to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required. These outputs are at current mode logic CML voltage levels. Single lane operation supports converter rates up to MSPS. The device supports two output modes that are selectable via the serial port interface SPI.


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  5. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining an bit output resolution. The device features an 8-lane, 15 Gbps JESDB data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency RF wireless applications. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator NCO for flexible, multiband frequency planning.

    The device supports up to a 1. Additionally, the AD supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3. The output current can be programmed from 8 mA to The DDS consists of a bank of 32, bit numerically controlled oscillators NCOs , each with its own phase accumulator. When combined with a MHz serial peripheral interface SPI and fast hop modes, phase coherent fast frequency hopping FFH is enabled, with several modes to support multiple applications.

    The device features an 8-lane, Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator NCO for flexible, frequency planning.

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    The device supports up to a MSPS complex data rate per input channel. The wide bandwidth of up to 1 GHz and the complex NCO and digital upconverter enable dual band and triple band direct RF synthesis of wireless infrastructure signals, eliminating costly analog upconverters. A serial peripheral interface SPI configures the AD and monitors the status of all the registers.

    The AD is a quad, bit, high dynamic range digital-to-analog converter DAC that provides a maximum sample rate of 2. Full-scale output current can be programmed over a typical range of The AD is a dual, bit, high dynamic range digital-to-analog converter DAC that provides a maximum sample rate of 2.